1. Field of the Invention
This invention relates to a semiconductor device and method of fabricating the same and more particularly, to a semiconductor device having an improved gate electrode or interconnection layer and a method of fabricating the same.
2. Description of the Prior Art
Complementary MOS type semiconductor devices, in particular, CMOS inverters, are conventionally fabricated by means of the following process.
Firstly, as shown in FIG. 1(a), a p-type well region 51 of approximately 5 micro-meter depth is formed in an n-type silicon (Si) substrate 50 having a crystal plane of (100). Impurity layers 52 and a oxidation layer 53 are formed for device isolation. Thus isolation regions 64 are formed. A gate dioxide layer 55 having a thickness between 10 nano-meter and 50 nano-meter, shown in FIG. 1(b), is fabricated in the device formation region by thermal oxidation. An n-type polycrystalline silicon layer is formed thereover and patterned by a photo-etching process to form gate electrode 56.
Next, n-channel MOS transistor source and drain regions 57 and potential extraction region 58 of substrate 50 are respectively formed by selective ion implantation of n-type impurities such as arsenic (As) ions. Then, p-type impurity ions, such as boron (B), are selectively implanted to form the source and drain regions of the p-channel MOS transistor and potential extraction region 60 of p-type well region 51. Subsequently, as shown in FIG. 1(c), a protective oxidation layer 61 is deposited by CVD (Chemical Vapour Deposition) method or the like. Contact holes are formed and an aluminum firing pattern 62 is formed.
The manufacturing processes used in the fabrication of the type of CMOS inverter described are the techniques widely used in the fabrication of conventional complementary metal oxide semiconductor devices.
Here, polycrystalline silicon is used as the firing material of gate electrode 56. Gate electrode 56 is used as a mask for forming the drain and source. The polysilicon is furthermore capable of withstanding subsequent heat treatment processing at extremely high temperatures.
The specific resistivity of the polycrystalline silicon has only decreased by 10.sup.-3 ohms cm, despite the introduction of high impurity concentrations. This has prevented high speed operation of a micropatterned element.
In view of this, in place of polycrystalline silicon, a two layer electrode structure formed of metal polycide comprised of polycrystalline silicon and metal silicide or molybdenum silicide which has a resistivity about 1/10 that of polysilicon has been used.
However, since the work function of these electrodes is constant regardless of ambient temperature and the work function of the channel region of the MOS transistor changes with changes in the ambient temperature, the difference of the mutual work function thereof increases in accordance with the changing ambient temperature. As a result, the threshold voltage temperature dependency of MOS transistors using these electrodes is greatly increased. This means that the fluctuation of threshold voltage for a given temperature variation is extremely increased. Thus, this greatly affects the stability of the MOS transistor's operating speed.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device and a method of fabricating the same in which the threshold voltage temperature dependency can be reduced by reducing the energy level degeneration of the electrode or interconnection layer which is comprised of either metal silicide or metal polycide of low resistivity.
A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first impurity region of second conductivity which is formed in the substrate, a second impurity region of the second conductivity type which is formed in the substrate and spaced apart from the first semiconductor region, a channel region located between the first and second impurity regions, an insulation layer on the channel region, and a gate electrode on the insulation layer including conductive layer means for decreasing the temperature dependence of the semiconductor device, the layer means including a conductive layer and a semiconductive layer for reducing energy level degeneration.
A method of fabricating a semiconductor device, comprising the steps of, selectively doping an impurity of a second conductivity type in a semiconductor substrate of a first conductivity type to form first and second impurity regions which are spaced apart so as to define a channel region therebetween, forming a gate insulation film on the substrate, forming a metal silicide layer containing a stoichiometrically excessive amount of silicon and impurity ion levels insufficient to cause an energy level degeneration on a portion of the gate insulation film which corresponds to the channel region, thereby providing a gate electrode, and annealing the metal silicide at a temperature not lower than the phase transformation temperature thereof for segregating a stoichiometrically excessive amount of silicon from the metal silicide at the interface between the metal silicide and the gate insulation film for reducing energy level degeneration thereof.